Semiconductor package

ABSTRACT

A semiconductor package includes a package substrate, a first semiconductor chip mounted on the package substrate and that includes a first semiconductor substrate that includes through electrodes, and a second semiconductor chip disposed on the first semiconductor chip and that includes a second semiconductor substrate that includes an active surface and an inactive surface. The second semiconductor chip further includes a plurality of isolated heat dissipation fins that extend in a vertical direction from the inactive surface.

CROSS-REFERENCE To RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 from Korean Patent Application No. 10-2021-0185403, filed on Dec. 22, 2021 in the Korean Intellectual Property Office, the contents of which are herein incorporated by reference in their entirety.

TECHNICAL FIELD

Embodiments of the inventive concept are directed to a semiconductor package, and more particularly, to a semiconductor package that includes a heat dissipation member.

DISCUSSION OF THE RELATED ART

Due to the demand for portable devices, electronic parts mounted in electronic products are being made smaller and lighter. To make electronic pans smaller and lighter, semiconductor packages mounted in the electronic parts are being gradually reduced in volume and process high capacity data. Thus, semiconductor chips mounted in a semiconductor package are highly integrated and single packaged. Therefore, a system in package (SiP) is used to efficiently arrange the semiconductor chips in a limited structure of a semiconductor package.

SUMMARY

Embodiments of the inventive concept are directed to a semiconductor package that has it heat dissipation characteristics and is more highly integrated by arranging a plurality of heat dissipation fins as heat dissipation members in an upper semiconductor chip in which a large amount of heat is generated.

According to an embodiment of the inventive concept, there is provided a semiconductor package that includes a package substrate, a first semiconductor chip mounted on the package substrate and that includes a first semiconductor substrate that includes through electrodes, and a second semiconductor chip disposed on the first semiconductor chip. The second semiconductor chip includes a second semiconductor substrate that include an active surface and an inactive surface, and the second semiconductor substrate includes a plurality of isolated heat dissipation fins that extend in a vertical direction from the inactive surface.

According to an embodiment of the inventive concept, there is provided a semiconductor package that includes a package substrate, a semiconductor chip stack mounted on the package substrate and that includes a plurality of semiconductor chips, and a molding member that surrounds the semiconductor chip stack. An uppermost semiconductor chip of the semiconductor chip stack includes a plurality of heat dissipation fins that have different lengths in a vertical direction. The remaining semiconductor chips in the semiconductor chip stack, excluding the uppermost semiconductor chip, include through electrodes, respectively.

According to an embodiment of the inventive concept, there is provided a semiconductor package that includes a package substrate, a first semiconductor chip mounted on the package substrate and that includes a first semiconductor substrate that includes a fin-shaped active area and a gate line that extends in a direction that intersects the fin-shaped active area, a second semiconductor chip disposed on the first semiconductor chip and that includes a second semiconductor substrate that includes a fin-shaped active area and a plurality of semiconductor patterns that are spaced apart from a top surface of the fin-shaped active area and that include a channel area, and a molding member that surrounds the first semiconductor chip and the second semiconductor chap on the package substrate. The first semiconductor chip includes through electrodes that penetrate through the first semiconductor substrate. The second semiconductor chip includes a plurality of isolated heat dissipation fins that extend in a vertical direction from the inactive surface of the second semiconductor substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1D each illustrates a semiconductor package according to an embodiment of the inventive concept.

FIGS. 2A and 2B each illustrates a semiconductor package according to an embodiment of the inventive concept.

FIGS. 3 to 6 are cross-sectional views of semiconductor packages according to an embodiment of the inventive concept.

FIGS. 7 to 10 are plan views of semiconductor packages according to an embodiment of the inventive concept.

FIG. 11 is a block diagram of an electronic device that includes a semiconductor package according to an embodiment of the inventive concept.

FIG. 12 is a block diagram of a semiconductor package according to an embodiment of inventive concept.

DETAILED DESCRIPTION

Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

FIGS. 1A to 1D each illustrates a semiconductor package 10 according to an embodiment of the inventive concept.

Specifically, FIG. 1A is a cross-sectional view of the semiconductor package 10, FIG. 1B is a plan view of the semiconductor package 10, FIG. 1C is an enlarged cross-sectional view of portion CC of FIG. 1A, and FIG. 1D is an enlarged cross-sectional view of portion DD of FIG. 1A. In addition, for convenience of illustration, in FIG. 1B a molding member 400 is illustrated as being transparent.

Referring to FIGS. 1A to 1D, in an embodiment, the semiconductor package 10 includes a first semiconductor chip 100, a second semiconductor chip 200, a package substrate 300, the molding member 400, and external connection terminals 500.

Each of the first and second semiconductor chips 100 and package 10 may be a logic chip or a memory chip. For example, both the first and second semiconductor chips 100 and 200 may be the same kind of memory chips, or one of the first and second semiconductor chips 100 and 200 may be a memory chip and the other may be a logic chip. In some embodiments, the first and second semiconductor chips 100 and 200 have a chiplet structure that includes a plurality of semiconductors.

The memory chip may be, for example, a volatile memory chip such as a dynamic random access memory (DRAM) or a static RAM (SRAM), or a non-volatile memory chip such as a phase-change RAM (PRAM), a magnetoresistive RAM (MRAM), a ferroelemic RAM (FeRAM), or a resistive RAM (RRAM). In addition, the logic chip may be, for example, one of a microprocessor, an analog device, or a digital signal processor.

The first semiconductor chip 100 includes a first substrate 101, a first semiconductor device layer 110, a first wiring layer 120, first bump pads 130, first through electrodes 150, and first upper pads 170.

The first substrate 101 is a semiconductor substrate and includes a top surface 101T and a bottom surface 101B that face each other. The top surface 101T may be referred to as an inactive surface and the bottom surface 101B may be referred to as an active surface. The first substrate 101 includes the first semiconductor device layer 110 formed on the bottom surface 101B and the first through electrodes 150 that penetrate the first substrate 101.

The first substrate 101 includes a silicon wafer that includes silicon (Si), such as at least one of crystalline silicon, polycrystalline silicon, or amorphous silicon. In an embodiment, the first substrate 101 includes a semiconductor element such as germanium (Ge) or a compound semiconductor such as one of silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). In an embodiment, the first substrate 101 has a silicon on insulator (SOI) structure. For example, the first substrate 101 includes a buried oxide (BOX) layer. The first substrate 101 includes a conductive area, such as a well doped with impurities or a structure doped with impurities. In addition, the first substrate 101 includes one of various isolation structures such as a shallow trench isolation (STI) structure.

Specifically, as illustrated in FIG. 1C, in an embodiment, the first semiconductor chip 100 includes fin type field effect transistors. Fin type active areas FA protrude from a top surface of the first substrate 101. The fin type active areas PA are spaced apart from each other in a first horizontal direction (an X direction) that extends parallel with the top surface of the first substrate 101, and extend in a second horizontal direction (a Y direction) perpendicular to the first horizontal direction (the X direction) and that extends parallel with the top surface of the first substrate 101. Away from the top surface of the first substrate 101 in a vertical direction (a Z direction), a width of each of the fin type active areas PA decreases in the first horizontal direction (the X direction). That is, the fin type active areas FA have a trapezoidal shape on the first substrate 101.

Device isolation layers 102 cover lower portions of both side walls of each of the fin type active areas FA on the first substrate 101. Although not shown, interfacial films that conformally cover the side walls of each of the fin type active areas FA are further formed between the device isolation layers 102 and the fin type active areas FA.

A gate dielectric layer 103 covers top surfaces of the fin type active areas FA and upper portions of both side walls of each of the fin type active areas FA on the device isolation layers 102. A gate dielectric layer 103 is interposed between the gate electrode 104 and the fin type active areas FA and between the gate electrode 104 and top surfaces of the device isolation layers 102. The gate dielectric layer 103 extends on a bottom surface and side walls of the gate electrode 104 in the first horizontal direction (X direction). The gate dielectric layer 103 includes a high dielectric layer that has a dielectric constant higher than that of silicon oxide, silicon oxynitride, silicon nitride, or a combination of the above compound semiconductors. The high dielectric layer includes a metal oxide or a metal oxynitride.

An interlayer insulating layer 105 covers a top surface of the gate electrode 104. The interlayer insulating layer 105 includes at least one of silicon oxide, silicon oxynitride, or silicon nitride.

Source/drain regions are arranged in the fin type active areas FA on both sides of the gate electrode 104. The source/drain regions include, for example, at least one of doped silicon germanium (SiGe), doped Ge, doped silicon carbide (SiC), or doped indium gallium arsenide (InGaAs). However, embodiments of the inventive concept are not necessarily limited thereto.

The first semiconductor device layer 110 is disposed on the bottom surface 101B of the first substrate 101. The first semiconductor device layer 110 includes the first wiring layers 120 that connect a plurality of semiconductor devices to other wiring lines formed in the first substrate 101. The first wiring layer 120 include metal wiring layers and via plugs. For example, the first wiring layer 120 have a multilayer structure in which two or more metal wiring layers or two or more via plugs are alternately stacked.

The first bump pads 130 are disposed on the first semiconductor device layer 110 and are electrically connected to the first wiring layer 120 in the first semiconductor device layer 110. The first bump pads 130 are disposed on a lower surface of the first semiconductor device layer 110 that is opposite to an upper surface of the first semiconductor device layer 110 that faces the bottom surface 101B of the first substrate 101. The first bump pads 130 are electrically connected to the first through electrodes 150 through the first wiring layer 120. The first bump pads 130 include at least one of aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), or gold (Au). However, embodiments of the inventive concept are not necessarily limited thereto.

In addition, a lower passivation layer is formed on the lower surface of the first semiconductor device layer 110. The lower passivation layer protects the first wiring layer 120 in the first semiconductor device layer 110 and other structures thereunder against external shock or moist. The lower passivation layer exposes top surfaces of the first bump pads 130.

The first through electrodes 150 penetrate the first substrate 101 from the top surface 101T of the first substrate 101 to the bottom surface 101B of the first substrate 101 in the vertical direction (the Z direction), and are connected to the first wiring layer 120 in the first semiconductor device layer 110. The first bump pads 130 are electrically connected to the first through electrodes 150 through the first wiring layer 120. At least some of the first through electrodes 150 are pillar-shaped. The first through electrodes 150 are through silicon vias (TSV).

First upper pads 170 that are electrically connected to the first through electrodes 150 are formed on the top surface 101T of the first substrate 101. The first upper pads 170 include substantially the same material as the first bump pads 130. In addition, an upper passivation layer surround parts of sides of the first upper pads 170 on the top surface 101T of the first substrate 101.

First bump structures BSI that contact the first bump pads 130 are disposed under the first semiconductor device layer 110. The first bump structures BSI electrically connect the semiconductor package 10 to the package substrate 300. Through the first bump structures BSI, the first semiconductor chip 100 receives at least one of a control signal, a power signal, or a ground signal for operating the first semiconductor chip 100, receives a data signal to be stored in the first semiconductor chip 100, or transmits data stored in the first semiconductor chip 100 to an external device. Each of the first bump structures BSI has one of a pillar structure, a ball structure, or a solder layer.

The second semiconductor chip 200 is disposed on the first semiconductor chip 100. The second semiconductor chip 200 includes a second substrate 201, a second semiconductor device layer 210, a second wiring layer 220, second bump pads 230, and a plurality of heat dissipation fins 250. The second substrate 201 includes a top surface 201T and a bottom surface 201B that face each other. The second semiconductor chip 200 is disposed so that the bottom surface 201B of the second substrate 201 faces the top surface 101T of the first substrate 101. The top surface 201T of second substrate 201 may be referred to as an inactive surface and the bottom surface 201B thereof may be referred to as an active surface. The second semiconductor chip 200 is electrically connected to the first semiconductor chip 100 through second bump structures BS2 interposed between the first semiconductor chip 100 and the second semiconductor chip 200.

In addition, an adhesive film AF is interposed between the top surface 101T of the first semiconductor chip 100 and the bottom surface 201B of the second semiconductor chip 200 and attaches the second semiconductor chip 200 to the first semiconductor chip 100. As illustrated in FIG. 1A, the adhesive film AF directly contacts the first semiconductor chip 100 and the second semiconductor chip 200 and surrounds the second bump structures BS2. The adhesive film AF is a die attach film. A die attach film includes an inorganic adhesive and a polymer adhesive. The polymer adhesive includes a thermosetting resin and a thermoplastic resin and may include a hybrid resin obtained by mixing the above two components with each other.

Because the second semiconductor chip 200 has characteristics that are the same as or similar to those of the first semiconductor chip 100, description will be given based on differences with the first semiconductor chip 100.

As illustrated in FIG. 1D, in an embodiment, the second semiconductor chip 200 include a gate all around (GAA) field effect transistor (FET) or a transistor (such as an MBCFET® (a multibridge channel FET)) that includes a nano-sheet.

Fin type active areas FA protrude from a top surface of the second substrate 201. The fin type active areas FA are spaced apart from one another in the first horizontal direction (the X direction) that extends parallel with the top surface of the second substrate 201 and extend in the second horizontal direction (the Y direction) perpendicular to the first horizontal direction (the X direction) and parallel with the top surface of the second substrate 201. Device isolation layers 202 that define the fin type active areas FA are formed in the second substrate 201.

A plurality of semiconductor patterns 200SP are spaced apart from the second substrate 201 in the vertical direction (the Z direction) on the fin type active areas FA. The plurality of semiconductor patterns 200SP include the same material as the second substrate 201. For example, the plurality of semiconductor patterns 200SP include a semiconductor such as Si or Ge, or a compound semiconductor such as SiGe, SiC, GaAs, InAs, or InP. In addition, each of the plurality of semiconductor patterns 200SP includes a channel region.

Each of the plurality of semiconductor patterns 200SP has a large width in the first horizontal direction (the X direction) and a small thickness in the vertical direction (the Z direction) and is shaped as, for example, a nanosheet. In some embodiments, each of the plurality of semiconductor patterns 200SP has a width in a range of about 5 nm to about 100 nm in the first horizontal direction (the X direction) or the second horizontal direction (the Y direction). However, embodiments of the inventive concept are not necessarily limited thereto.

Gate dielectric layers 203 are interposed between a gate electrode 204 and the plurality of semiconductor patterns 200SP. The gate dielectric layers 203 are conformally formed on external walls of the plurality of semiconductor patterns 200SP. The gate electrode 204 extends on the fin type active areas FA and the device isolation layers 202 while surrounding the plurality of semiconductor patterns 200SP on the fin type active areas FA.

An interlayer insulating layer 205 covers a top surface of the gate electrode 204. The interlayer insulating layer 205 includes at least one of silicon oxide, silicon oxynitride, or silicon nitride.

Source/drain regions are formed in the fin type active areas FA on both sides of each of the plurality of semiconductor patterns 200SP and are connected to both ends of each of the plurality of semiconductor patterns 200SP.

The second semiconductor device layer 210 is formed on the active bottom surface 201B of the second semiconductor chip 200. The second bump pads 230 are disposed on the bottom surface of the second semiconductor device layer 210 and are electrically connected to the second wiring layer 220 in the second semiconductor device layer 210. The second hump pads 230 are electrically connected to the second semiconductor device layer 210 through the second wiring layer 220. The second bump pads 230 include substantially the same material as the first bump pads 130.

Second bump structures BS2 contact the second bump pads 230. Through the second bump structures BS2, the second semiconductor chip 200 receives at least one of a control signal, a power signal, or a ground signal for operating the second semiconductor chip 200, receives a data signal to be stored in the second semiconductor chip 200, or transmits data stored in the second semiconductor chip 200.

In the semiconductor package 10 according to an embodiment of the inventive concept, the second substrate 201 includes the plurality of isolated heat dissipation fins 250 in the second substrate 201 that extend in the vertical direction (the Z direction) from the top surface 201T of the second semiconductor chip 200. The plurality of heat dissipation fins 250 include first heat dissipation fins 251 and second heat dissipation fins 252 in accordance with their formation positions.

The plurality of heat dissipation fins 250 include a thermally conductive material. The plurality of heat dissipation fins 250 include substantially the same material as the first through electrodes 150 of the first semiconductor chip 100. Unlike the first through electrodes 150, each of the plurality of heat dissipation fins 250 electrically floats. The plurality of heat dissipation fins 250 include, for example, at least one of Cu, Al, titanium (Ti), tantalum (Ta), W, or Ni, or a combination of the above metals.

The plurality of heat dissipation fins 250 emit heat generated by the second semiconductor chip 200. For this purpose, top surfaces of the plurality of heat dissipation fins 250 are exposed from the second substrate 201. For example, a level of the top surface of each of the plurality of heat dissipation fins 250 is substantially coplanar with the inactive top surface 201T of the second substrate 201. The top surfaces of the plurality of heat dissipation fins 250 are square-shaped. For example, the plurality of heat dissipation fins 250 are square pillar-shaped.

Referring to FIG. 1B, in an embodiment, the second semiconductor chip 200 includes an active area 200AR in which active transistors are arranged and a dummy area 200DR in which dummy transistors are arranged. A first distribution density of first heat dissipation fins 251 in the active area 200AR is less than a second distribution density of second heat dissipation fins 252 in the dummy area 200DR.

In addition, a first length 251H in the vertical direction (the Z direction) of each of the first heat dissipation fins 251 in the active area 200AR is greater than a second length 252H in the vertical direction (the Z direction) of each of the second heat dissipation fins 252 in the dummy area 200DR. For example, a first vertical distance between each of the first heat dissipation fins 251 in the active area 200AR and each of the active transistors is less than a second vertical distance between each of the second heat dissipation fins 252 in the dummy area 200DR and each of the dummy transistors.

Therefore, heat generated by the active area 200AR is effectively emitted from the second semiconductor chip 200 through the first heat dissipation fins 251 and through the second heat dissipation fins 252 in the dummy area 200DR.

The package substrate 300 includes a substrate base 301, an upper protective layer, and a lower protective layer as a supporting substrate. The package substrate 300 includes one or more of a printed circuit board (PCB), a wafer substrate, a ceramic substrate, or a glass substrate. In the semiconductor package 10 according to the inventive concept, the package substrate 300 includes a PCB.

The external connection terminals 500 are disposed under lower electrode pads 310 that are disposed in a bottom surface of the package substrate 300. The semiconductor package 10 is electrically connected to and mounted in a module substrate or a system board of an electronic product through the external connection terminals 500, which will be described in detail below with reference to FIG. 11 . In addition, a wiring line 320 is formed in the package substrate 300 and the wiring line 320 connects the lower electrode pads 310 to upper electrode pads 330 disposed in a top surface of the package substrate 300.

The wiring line 320 may have a multilayer or single layer structure formed in the substrate base 301, and the external connection terminals 500 are electrically connected to the first semiconductor chip 100 through the wiring line 320. The upper protective layer and the lower protective layer protect the substrate base 301, and include, for example, a solder resist.

When the package substrate 300 includes a PCB, the substrate base 301 is implemented by compressing a polymer material such as a thermosetting resin, an epoxy based resin such as flame retardant 4 (FR-4), bismaleimide triazine (BT), or ajinomoto build up film (ABF), or a phenol resin to a constant thickness, coating copper foil on both sides of the resin, and performing patterning to form the wiring line 320. Top and bottom surfaces of the substrate base 301, excluding the lower electrode pads 310 and the upper electrode pads 330, are coated with solder resist so that the upper protective layer and the lower protective layer can be implemented.

The PCB includes a single layer PCB on which the wiring line 320 is formed on one surface thereof, and a double layer PCB in which the wiring line 320 is formed on both surfaces thereof. in addition, three or more layers of copper foil are formed by using an insulator called prepreg and, by forming three or more wiring lines 320 in accordance with the number of layers of the copper foil, a multilayered PCB can be implemented. The package substrate 300 is not necessarily limited to the above-described structure or PCB material.

A molding member 400 is disposed on the first and second semiconductor chips 100 and 200 that protects the first and second semiconductor chips 100 and 200 against external influences such as contamination and shock. To perform this role, a thickness of the molding member 400 is determined so that the molding member 400 covers at least the first and second semiconductor chips 100 and 200. Because the molding member 400 covers all of the package substrate 300, a width of the molding member 400 is substantially equal to a width of the semiconductor package 10.

In addition, the molding member 400 includes, for example, an epoxy molding compound EMC). The molding member 400 may include one of various materials, such as an epoxy based material, a thermosetting material, a thermoplastic material, or an ultraviolet (UV) processing material without being limited to the EMC.

A proper amount of molding resin is implemented onto the package substrate 300 by an implantation process and an appearance of the semiconductor package 10 is formed by a hardening process. The appearance of the semiconductor package 10 is formed by applying pressure to the molding resin in a pressing process. Process conditions, such as delay time between implantation of the molding resin and pressure, an amount of the implanted molding resin, and pressurization temperature/pressure are set considering physical characteristics such as viscosity of the molding resin.

An underfill is formed between the first semiconductor chip 100 and the package substrate 300. A gap may be formed between the first semiconductor chip 100 and the package substrate 300. Because the gap can deteriorate connection reliability between the first semiconductor chip 100 and the package substrate 300, the underfill 410 is implanted to reinforce the connection between the first semiconductor chip 100 and the package substrate 300. In an embodiment, the underfill 410 is omitted and a molded underfill (MUF) process is used instead.

To make electronic parts mounted in electronic products smaller and lighter, the semiconductor package 10 mounted in each of the electronic parts has a reduced volume and can process high capacity data. The first and second semiconductor chips 100 and 200 mounted in the semiconductor package 10 are highly integrated and single packaged. Therefore, a system in package (SiP) is used to efficiently arrange the first and second semiconductor chips 100 and 200 in a limited structure of the semiconductor package 10. However, because a large amount of heat is commonly generated by the operations of a processor chip, chip performance can deteriorate unless generation of heat is controlled.

Therefore, in the semiconductor package 10 according to an embodiment of the inventive concept, by arranging the plurality of heat dissipation fins 250 as heat dissipation members in the second semiconductor chip 200, which generates a greater amount of heat than he first semiconductor chip 100, the semiconductor chips can be efficiently arranged in a limited spatial structure of the semiconductor package 10 and an environment is provided that is advantageous to heat emission characteristics and high integration.

FIGS. 2A and 2B illustrate a semiconductor package 20 according to an embodiment of the inventive concept.

Specifically, FIG. 2A is a cross-sectional view of the semiconductor package 20 and FIG. 2B is a plan view of the semiconductor package 20. In addition, for convenience of illustration in FIG. 2B, a molding member 400 is illustrated as being transparent.

Most components that constitute the semiconductor package 20 described hereinafter and materials that constitute the below-described components are substantially the same as or similar to those described with reference to FIGS. 1A to 1D. Therefore, for convenience of description, descriptions will focus differences with the above-described semiconductor package 10.

Referring to FIGS. 2A and 2B, in an embodiment, the semiconductor package 20 includes a first semiconductor chip 100, a second semiconductor chip 200, a package substrate 300, a molding member 400, and external connection terminals 500.

In the semiconductor package 20 according to an embodiment, a second substrate 201 includes an isolated heat dissipation member 250A that extends in the vertical direction the Z. direction) from a top surface 201T of the second substrate 201. The heat dissipation member 250A includes first heat dissipation fins 251 and second heat dissipation fins 252 in accordance with formation positions and a heat dissipation bridge 253 that connects the first heat dissipation fins 251 to the second heat dissipation fins 252 in the first and second horizontal directions (the X and Y directions) in the form of a net.

The heat dissipation member 250A emits heat generated by the second semiconductor chip 200. A top surface of the heat dissipation member 250A is exposed from the second substrate 201. For example, a level of a top surface of the heat dissipation bridge 253 is substantially coplanar with the inactive top surface 201T of the second substrate 201.

The second semiconductor chip 200 includes an active area 200AR in which active transistors are arranged and a dummy area 200DR in which dummy transistors are arranged. A first distribution density of the first heat dissipation fins 251 in the active area 200AR is less than a second distribution density of the second heat dissipation fins 252 in the dummy area 200DR.

In addition, a first length in the vertical direction (the Z direction) of each of the first heat dissipation fins 251 in the active area 200AR is greater than a second length in the vertical direction (the Z direction) of each of the second heat dissipation fins 252 in the dummy area 200DR. For example, a first vertical distance between each of the first heat dissipation fins 251 in the active area 200AR and each of the active transistors is less than a second vertical distance between each of the second heat dissipation fins 252 in the dummy area 200DR and each of the dummy transistors.

Therefore, heat generated by the active area 200AR is effectively emitted from the second semiconductor chip 200 by the heat dissipation member 250A through the first heat dissipation fins 251 and the second heat dissipation fins 252 in the dummy area 200DR.

FIGS. 3 to 6 are cross-sectional views of semiconductor packages 30, 40, 50, and 60 according to embodiments of the inventive concept.

Most components that constitute the semiconductor packages 30, 40, 50, and 60 described hereinafter and materials that constitute the below-described components are substantially the same as or similar to those described with reference to FIGS. 1A to 1D. Therefore, for convenience of description, description will focus on differences with the above-described semiconductor package 10.

Referring to FIG. 3 , in an embodiment, the semiconductor package 30 includes a first lower semiconductor chip 100L, a first upper semiconductor chip 100U, a second semiconductor chip 200, a package substrate 300, a molding member 400, and external connection terminals 500.

In the semiconductor package 30 according to an embodiment, each of the first lower semiconductor chip 100L, the first upper semiconductor chip 100U, and the second semiconductor chip 200 includes a high bandwidth memory (HBM) chip.

FIG. 3 shows that the first lower semiconductor chip 100L, the first upper semiconductor chip 100U, and the second semiconductor chip 200 of the semiconductor package 30 are stacked. However, the number of semiconductor chips stacked in the semiconductor package 30 is not necessarily limited thereto. For example, in some embodiments, four or more semiconductor chips are stacked in the semiconductor package 30.

The first lower semiconductor chip 100L and the first upper semiconductor chip 100U have substantially the same structure. However, the first lower semiconductor chip 100L is electrically connected to the package substrate 300 through first bump structures BS1 and the first upper semiconductor chip 100U is electrically connected to the first lower semiconductor chip 100L through second bump structures BS2.

The second semiconductor chip 200 is mounted on a top surface of the first upper semiconductor chip 100U. The second semiconductor chip 200 is electrically connected to the first upper semiconductor chip 100U through third bump structures BS3 interposed between the first upper semiconductor chip 100U and the second semiconductor chip 200.

In addition, an adhesive film AF that attaches the second semiconductor chip 200 to the first upper semiconductor chip 100U is interposed between the top surface of the first upper semiconductor chip 100U and a bottom surface of the second semiconductor chip 200. As illustrated in FIG. 3 , the adhesive film AF directly contacts the first upper semiconductor chip 100U and the second semiconductor chip 200 and surrounds the third bump structures BS3.

In the semiconductor package 30 according to an embodiment of the inventive concept, a second substrate 201 of the second semiconductor chip 200 in the uppermost portion includes a plurality of isolated heat dissipation fins 250 that extend in the vertical direction (the Z direction) from a top surface 201T of the second semiconductor chip 200. The plurality of heat dissipation fins 250 include first heat dissipation fins 251 and second heat dissipation fins 252 in accordance with formation positions. Each of the first heat dissipation fins 251 has a length that differs from that of each of the second heat dissipation fins 252.

Referring to FIG. 4 , in an embodiment, the semiconductor package 40 includes a first lower semiconductor chip 100L, a first upper semiconductor chip 100U, a second semiconductor chip 200, a package substrate 300, a molding member 400, and external connection terminals 500.

Components of the semiconductor package 40 according to an embodiment are substantially the same as those of the semiconductor package 30 of FIG. 3 . Therefore, description will focus differences with the semiconductor package 30 of FIG. 3 .

A second substrate 201 of the second semiconductor chip 200 in the uppermost portion includes an isolated heat dissipation member 250A that extends in the vertical direction (the Z direction) from a top surface 201T of the second semiconductor chip 200. The heat dissipation member 250A includes first heat dissipation fins 251 and second heat dissipation fins 252 in accordance with formation positions and a heat dissipation bridge 253 that connects the first heat dissipation fins 251 to the second heat dissipation fins 252 in the first and second horizontal directions (the X and Y directions) in the form of a net.

The heat dissipation member 250A emits heat generated by the second semiconductor chip 200. For this purpose, a top surface of the heat dissipation member 250A is exposed from the second substrate 201. For example, a level of a top surface of the beat dissipation bridge 253 is substantially coplanar with the inactive top surface 201T of the second substrate 201.

Referring to FIG. 5 , in an embodiment, the semiconductor package 50 includes a first semiconductor chip 100, a second semiconductor chip 200, a package substrate 300, a molding member 400, and external connection terminals 500.

In the semiconductor package 50 according to an embodiment, a second substrate 201 includes a plurality of isolated heat dissipation members 250B that extend in the vertical direction. (the Z direction) from a top surface 201T of the second semiconductor chip 200.

The plurality of heat dissipation fins 250B emit heat generated by the second semiconductor chip 200. For this purpose, top surfaces of the plurality of beat dissipation tins 250B are exposed from the second substrate 201. For example, a level of the top surface of each of the plurality of heat dissipation tins 250B is substantially coplanar with the inactive top surface 201T of the second substrate 201.

The second semiconductor chip 200 includes an active area in which active transistors are arranged and a dummy area in which dummy transistors are arranged. The plurality of heat dissipation fins 250B in the active area and the dummy area have substantially the same distribution density.

In addition, the plurality of heat dissipation fins 250B in the active area and the dummy area have substantially the same length 250H in the vertical direction the Z direction). For example, a vertical distance between each of the plurality of heat dissipation fins 250B in the active area and each of the active transistors is substantially equal to a vertical distance between each of the plurality of heat dissipation fins 250B in the dummy area and each of the dummy transistors.

Referring to FIG. 6 , in an embodiment, the semiconductor package 60 includes a first semiconductor chip 100, a second semiconductor chip 200, a package substrate 300, a molding member 400, and external connection terminals 500.

In the semiconductor package 60 according to an embodiment, a second substrate 201 includes an isolated heat dissipation member 250C that extends in the vertical direction (the Z direction) from a top surface 201T of the second semiconductor chip 200.

The heat dissipation member 2500 includes a plurality of first heat dissipation fins 251 that have the same shape regardless of formation positions and a heat dissipation bridge 253 that connect the plurality of first heat dissipation fins 251 to each other in the first and second horizontal directions (the X and Y directions) in the form of a net.

The heat dissipation member 250C emits heat generated by the second semiconductor chip 200. For this purpose, a top surface of the heat dissipation member 250C is exposed from the second substrate 201. For example, a level of a top surface of the heat dissipation bridge 253 is substantially coplanar with the inactive top surface 201T of the second substrate 201.

The second semiconductor chip 200 includes an active area in which active transistors are arranged and a dummy area in which dummy transistors are arranged. The plurality of first heat dissipation fins 251 in the active area and the dummy area have substantially the same distribution density.

In addition, the plurality of first heat dissipation fins 251 in the active area and the dummy area have substantially the same length in the vertical direction (the Z direction). For example, a vertical distance between each of the first heat dissipation fins 251 in the active area and each of the active transistors is substantially equal to a vertical distance between each of the first heat dissipation fins 251 and each of the dummy transistors.

FIGS. 7 to 10 are plan views of semiconductor packages 70, 80, 90, and 95 according, to embodiments of the inventive concept.

Most components that constitute the semiconductor packages 70, 80, 90, and 95 described hereinafter and materials that constitute the below-described components are substantially the same as or similar to those described with reference to FIGS. 1A to 1D. Therefore, for convenience of description, description will focus on differences with the above-described semiconductor package 10.

Referring to FIG. 7 , in an embodiment, the semiconductor package 70 includes a first semiconductor chip, a second semiconductor chip 200, a package substrate 300, a molding member, and external connection terminals.

In the semiconductor package 70 according to an embodiment, the second semiconductor chip 200 includes a plurality of isolated heat dissipation fins 250D that extend in the vertical direction (the Z direction) from a top surface of the second semiconductor chip 200. The plurality of heat dissipation fins 250D include first heat dissipation fins 251 and second heat dissipation fins 252 in accordance with formation positions.

The plurality of heat dissipation fins 250D emit heat generated by the second semiconductor chip 200. For this purpose, top surfaces of the plurality of heat dissipation fins 250D are exposed from the second semiconductor chip 200. In an embodiment, the top surfaces of the plurality of heat dissipation fins 250D are circular. For example, the plurality of heat dissipation fins 250D are cylindrical. In an embodiment, the top surfaces of the plurality of heat dissipation fins 250D are polygonal. For example, the plurality of heat dissipation fins 250D have a polygonal-pillar shape.

Referring to FIG. 8 , in an embodiment, the semiconductor package 80 includes a first semiconductor chip, a second semiconductor chip 200, a package substrate 300, a molding member, and external connection terminals.

In the semiconductor package 80 according to an embodiment, the second semiconductor chip 200 includes a plurality of isolated heat dissipation fins 250E that extend in the vertical direction (the Z direction) from a top surface of the second semiconductor chip 200. The plurality of heat dissipation fins 250E include first heat dissipation fins 251 and second heat dissipation fins 252 in accordance with formation positions.

The plurality of heat dissipation fins 250E emit heat generated by the second semiconductor chip 200. For this purpose, top surfaces of the plurality of heat dissipation fins 250E are exposed from the second semiconductor chip 200. For example, the top surfaces of the plurality of heat dissipation fins 250E are alternately circular and square-shaped. For example, rows of the plurality of heat dissipation fins 250E alternately have a cylindrical or a square pillar shape.

Referring to FIG. 9 , in an embodiment, the semiconductor package 90 includes a first semiconductor chip, a second semiconductor chip 200, a package substrate 300, a molding member, and external connection terminals.

In the semiconductor package 90 according to an embodiment, the second semiconductor chip 200 includes an isolated heat dissipation member 250F that extends in the vertical direction (the Z direction) from a top surface of the second semiconductor chip 200. The heat dissipation member 250F includes first heat dissipation fins 251 and second heat dissipation fins 252 in accordance with formation positions, and a heat dissipation bridge 253 that connects the first heat dissipation fins 251 to the second heat dissipation fins 252 in the form of a straight line that extends in one of the first or second horizontal directions (the X and Y directions).

The heat dissipation member 250F emits heat generated by the second semiconductor chip 200. For this purpose, a top surface of the heat dissipation bridge 253 is exposed from the second semiconductor chip 200.

Referring to FIG. 10 , in an embodiment, the semiconductor package 95 includes a first semiconductor chip, a second semiconductor chip 200, a package substrate 300, a molding member, and external connection terminals.

In the semiconductor package 95 according to an embodiment, an active area 200AR of the second semiconductor chip 200 includes a first active area 200AR1 and a second active area 200AR2 that are apart from each other.

The second semiconductor chip 200 includes an active area 200AR in which active transistors are arranged and a dummy area 200DR in which dummy transistors are arranged. A first distribution density of the first heat dissipation fins 251 in the active area 200AR is less than a second distribution density of the second heat dissipation fins 252 in the dummy area 200DR.

The first active area 200AR1 and the second active area 200AR2 are spaced apart from each other with the center point of the top surface of the second semiconductor chip 200 therebetween. In addition, the first active area 200AR1 and the second active area 200AR2 are diagonally offset from each other in the top surface of the second semiconductor chip 200. However, embodiments of the inventive concept are not necessarily limited thereto.

FIG. 11 is a block diagram of an electronic device 1000 that includes a semiconductor package according to an embodiment of the inventive concept.

Referring to FIG. 11 , in an embodiment, the electronic device 1000 accommodates a main board 1010. A chipset 1020, a network 1030, and other components 1040 are physically and/or electrically connected to the main board 1010. The chipset 1020, the network 1030, and the other components 1040 are also combined with other electronic components described below to form various signal lines 1090.

The chipset 1020 includes a memory chip such as volatile memory, non-volatile memory, or flash memory, an application processor chip such as a central processor, a graphics processor, a digital signal processor, an encryption processor, a microprocessor, or a microcontroller, and a logic chip such as an analog-to-digital (AD) converter or an application-specific integrated circuit (ASIC). In addition, other forms of chip related electronic components may be included. In addition, the components of the chipset 1020 may be combined with one another.

The network 1030 may be one of a WiFi (IEEE 802.11 family, etc.), a WiMAX (IEEE 802.16 family, etc.), an IEEE 802.20, a long term evolution (LTE), an Ev-DO, an HSPA+, an HSDPA+, an HSUPA+, an EDGE, a GPS, a GPRS, a CDMA, a TDMA, a DECT, a Bluetooth, a 3G, a 4G, a 5G, or any other wired/wireless protocols designated as follows. In addition, any of a plurality of other wired/wireless standards and protocols may be included. In addition, the network 1030 may be combined with the chipset 1020.

The other components 1040 include a high frequency inductor, a ferrite inductor, a power inductor, ferrite beads, low temperature co-firing ceramics (LTCC), an electro-magnetic interference (EMI) filter, and/or a multi-layer ceramic condenser (MLCC). In addition, a manual component that is used for various other purposes may be included. In addition, the other components 1040 may be combined with the chipset 1020 and/or the network 1030.

In accordance with the type of the electronic device 1000, the electronic device 1000 may include other electronic components that may be or may not be physically and/or electrically connected to the main board 1010. The other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a bulk storage, a compact disk (CD), and/or a digital versatile disk (DVD). In addition, in accordance with the type of the electronic device 1000, electronic components that are used for various purposes may be included.

The electronic device 1000 may be a smartphone, a personal digital assistant (PDA), a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop computer, a netbook, a television, a video game, or a smart watch. The electronic device 1000 may include any other electronic device that processes data.

The semiconductor packages 10, 20, 30, 40, 50, 60, 70, 80, 90, and 95 according to embodiments of the inventive concept described with reference to FIGS. 1A to 10 are incorporated into the electronic device 1000 for various purposes.

FIG. 12 is a block diagram of a semiconductor package 1100 according to an embodiment of the inventive concept.

Referring to FIG. 12 , in an embodiment, the semiconductor package 1100 include a micro-processing unit (MPU) 1110, a memory 1120, an interface 1130, a graphics processing unit (GPU) 1140, function blocks 1150, and a bus 1160 connecting the above components to one another.

The semiconductor package 1100 may include both the MPU 1110 and the GPU 1140 or may include only one of the MPU 1110 or the GPU 1140.

The MPU 1110 may include a core and a cache. For example, the MPU 1110 may include a multicore. Cores of a multicore may have the same performance or different performances. In addition, the cores of a multicore may be simultaneously activated or may be activated at different times.

The memory 1120 stores a result processed by the function blocks 1150 under control of the MPU 1110. The interface 1130 exchanges information or signals with external devices. The GPU 1140 performs graphics functions. For example, the GPU 1140 can perform a video codec or process 3D graphics. The function blocks 1150 perform various functions. For example, when the semiconductor package 1100 is an application processor for a mobile device, some of the function blocks 1150 perform a communication function.

The semiconductor package 1100 includes one of the semiconductor packages 10, 20, 30, 40, 50, 60, 70, 80, 90, and 95 according to embodiments of the inventive concept described with reference to FIGS. 1A to 10 .

While embodiments of the inventive concept have been particularly shown and described with reference to the figures, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims. 

What is claimed is:
 1. A semiconductor package, comprising: a package substrate; a first semiconductor chip mourned on the package substrate, wherein the first semiconductor chip includes a first semiconductor substrate that includes through electrodes; and a second semiconductor chip disposed on the first semiconductor chip, wherein the second semiconductor chip includes a second semiconductor substrate that includes an active surface and an inactive surface, and the second semiconductor substrate includes a plurality of isolated heat dissipation fins that extend from the inactive surface in a vertical direction.
 2. The semiconductor package of claim 1, wherein the second semiconductor chip comprises an active area in which active transistors are arranged and a dummy area in which dummy transistors are arranged, and wherein a first distribution density of the plurality of heat dissipation fins in the active area is less than a second distribution density of the plurality of heat dissipation fins in the dummy area.
 3. The semiconductor package of claim 2, wherein a first length in the vertical direction of each of the plurality of heat dissipation fins in the active area is greater than a second length in the vertical direction of each of the plurality of heat dissipation fins in the dummy area.
 4. The semiconductor package of claim 3, wherein a first vertical distance between each of the plurality of heat dissipation fins in the active area and each of the active transistors is less than a second vertical distance between each of the plurality of heat dissipation fins in the dummy area and each of the dummy transistors.
 5. The semiconductor package of claim 2, wherein upper portions of the plurality of heat dissipation fins are connected in horizontal directions to a heat dissipation bridge in a form of a net, and wherein a level of a top surface of the heat dissipation bridge is substantially coplanar with the inactive surface of the second semiconductor substrate.
 6. The semiconductor package of claim 5, wherein heat generated by the active area is emitted from the second semiconductor chip through the plurality of heat dissipation fins in the dummy area.
 7. The semiconductor package of claim 2, wherein upper portions of the plurality of heat dissipation fins are connected to a heat dissipation bridge in a form of a straight line that extends in one of horizontal directions, and wherein a level of a top surface of the heat dissipation bridge is substantially coplanar with the inactive surface of the second semiconductor substrate.
 8. The semiconductor package of claim 1, wherein the first semiconductor chip comprises through electrodes that penetrate through the first semiconductor substrate.
 9. The semiconductor package of claim 8, wherein the plurality of heat dissipation fins include substantially a same material as the through electrodes, wherein each of the plurality of heat dissipation fins electrically floats, and wherein the through electrodes electrically connect the first semiconductor chip to the second semiconductor chip.
 10. The semiconductor package of claim 1, wherein a first transistor in the first semiconductor chip is a fin-shaped field effect transistor (FET), and wherein a second transistor in the second semiconductor chip is a gate all around (GAA)-shaped FET.
 11. A semiconductor package, comprising: a package substrate; a semiconductor chip stack mounted on the package substrate and that includes a plurality of semiconductor chips; and a molding member that surrounds the semiconductor chip stack, wherein an uppermost semiconductor chip of the semiconductor chip stack comprises a plurality of heat dissipation fins that have different lengths in a vertical direction, and wherein, remaining semiconductor chips in the semiconductor chip stack, excluding the uppermost semiconductor chip, comprise through electrodes, respectively.
 12. The semiconductor package of claim 11, wherein the uppermost semiconductor chip comprises an active area in which active transistors are arranged and a dummy area in which dummy transistors are arranged, and wherein a first length in the vertical direction of each of the plurality of heat dissipation fins in the active area is greater than a second length in the vertical direction of each of the plurality of heat dissipation fins in the dummy area.
 13. The semiconductor package of claim 11, wherein a vertical level of top surfaces of the plurality of heat dissipation fins is substantially coplanar with a top surface of the uppermost semiconductor chip.
 14. The semiconductor package of claim 11, wherein the plurality of heat dissipation fins include substantially a same material as the through electrodes, wherein each of the plurality of heat dissipation fins electrically floats, and wherein the through electrodes electrically connect the plurality of semiconductor chips to each other.
 15. The semiconductor package of claim 11, wherein the semiconductor chip stack comprises high bandwidth memory (HBM) chips.
 16. A semiconductor package, comprising: a package substrate; a first semiconductor chip mounted on the package substrate and that includes a first semiconductor substrate that includes a fin-shaped active area and a gate line that extends in a direction that intersects the fin-shaped active area; a second semiconductor chip disposed on the first semiconductor chip and that includes a second semiconductor substrate that includes a fin-shaped active area and a plurality of semiconductor patterns that are spaced apart from a top surface of the fin-shaped active area and that include a channel area; and a molding member that surrounds the first semiconductor chip and the second semiconductor chip on the package substrate, wherein the first semiconductor chip comprises through electrodes that penetrate through the first semiconductor substrate, and wherein the second semiconductor substrate comprises a plurality of isolated heat dissipation fins that extend in a vertical direction from the inactive surface of the second semiconductor substrate.
 17. The semiconductor package of claim 16, wherein the second semiconductor chip comprises an active area in which is disposed a GAA-shaped FET that includes the plurality of semiconductor patterns, and a dummy area in which is disposed a dummy transistor, and wherein a first distribution density of the plurality of heat dissipation fins in the active area is less than a second distribution density of the plurality of heat dissipation fins in the dummy area.
 18. The semiconductor package of claim 17, wherein upper portions of the plurality of heat dissipation fins are connected to a heat dissipation bridge in horizontal directions in a form of a net, and wherein heat generated by the active area is emitted from the second semiconductor substrate to the dummy area through the plurality of heat dissipation fins connected to each other.
 19. The semiconductor package of claim 16, wherein the plurality of heat dissipation fins have a cylindrical pillar shape, a square pillar shape, or a polygonal pillar shape.
 20. The semiconductor package of claim 17, wherein the active area comprises a first active area and a second active area that are apart from each other, wherein the first semiconductor chip and the second semiconductor chip comprise different types of semiconductor devices, and wherein the second semiconductor chip comprises a logic element. 